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| a FEATURES 3 V/5 V Power Supply 25 MHz Speed On-Chip SINE Look-Up Table On-Chip 10-Bit DAC Parallel Loading Powerdown Option 72 dB SFDR 125 mW (5 V) Power Consumption 40 mW (3 V) Power Consumption 48-Pin TQFP APPLICATIONS DDS Tuning Digital Demodulation GENERAL DESCRIPTION CMOS Complete DDS AD9831 This DDS device is a numerically controlled oscillator employing a phase accumulator, a sine look-up table and a 10-bit D/A converter integrated on a single CMOS chip. Modulation capabilities are provided for phase modulation and frequency modulation. Clock rates up to 25 MHz are supported. Frequency accuracy can be controlled to one part in 4 billion. Modulation is effected by loading registers through the parallel microprocessor interface. A powerdown pin allows external control of a powerdown mode. The part is available in a 48-pin TQFP package. FUNCTIONAL BLOCK DIAGRAM DVDD DGND AVDD AGND REFOUT FS ADJUST REFIN MCLK FSELECT FREQ0 REG MUX FREQ1 REG ON-BOARD REFERENCE FULL-SCALE CONTROL COMP PHASE ACCUMULATOR (32-BIT) 12 SIN ROM 10-BIT DAC IOUT PHASE0 REG PHASE1 REG PHASE2 REG PHASE3 REG MUX AD9831 PARALLEL REGISTER SLEEP TRANSFER CONTROL RESET MPU INTERFACE D0 D15 WR A0 A1 A2 PSEL0 PSEL1 REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. (c) Analog Devices, Inc., 1996 One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703 10%; AD9831-SPECIFICATIONS1 (V = +3.3 V= 3.9 k +5R V REFOUT; R ; DD SET LOAD 10%; AGND = DGND = 0 V; TA = TMIN to TMAX; REFIN = = 300 for IOUT unless otherwise noted) Test Conditions/Comments Parameter SIGNAL DAC SPECIFICATIONS Resolution Update Rate (fMAX) IOUT Full Scale Output Compliance DC Accuracy Integral Nonlinearity Differential Nonlinearity DDS SPECIFICATIONS2 Dynamic Specifications Signal to Noise Ratio Total Harmonic Distortion Spurious Free Dynamic Range (SFDR)3 Narrow Band ( 50 kHz) Wide Band ( 2 MHz) Clock Feedthrough Wake-Up Time4 Powerdown Option VOLTAGE REFERENCE Internal Reference @ +25C TMIN to TMAX REFIN Input Impedance Reference TC REFOUT Output Impedance LOGIC INPUTS VINH, Input High Voltage VINL, Input Low Voltage IINH, Input Current CIN, Input Capacitance POWER SUPPLIES AVDD DVDD IAA IDD IAA + IDD5 Low Power Sleep Mode6 AD9831A 10 25 4 5 1.5 1 0.5 Units Bits MSPS nom mA nom mA max V max LSB typ LSB typ 50 -53 -72 -70 -50 -60 1 Yes 1.21 1.21 7% 10 100 300 VDD - 0.9 0.9 10 10 2.97/5.5 2.97/5.5 12 2.5 + 0.33/MHz 15 24 1 dB min dBc max dBc min dBc min dBc min dBc typ ms typ fMCLK = 25 MHz, fOUT = 1 MHz fMCLK = 25 MHz, fOUT = 1 MHz fMCLK = 6.25 MHz, fOUT = 2.11 MHz 5 V Power Supply 3 V Power Supply Volts typ Volts min/max M typ ppm/C typ typ V min V max A max pF max V min/V max V min/V max mA max mA typ mA max mA max mA max 5 V Power Supply 5 V Power Supply 3 V Power Supply 5 V Power Supply 1 M Resistor Tied Between REFOUT and AGND NOTES 1 Operating temperature range is as follows: A Version: -40C to +85C. 2 100% production tested. 3 fMCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, f OUT = 2.11 MHz. 4 See Figure 11. To reduce the wake-up time at low power supplies and low temperature, the use of an external reference is suggested. 5 Measured with the digital inputs static and equal to 0 V or DVDD. 6 The Low Power Sleep Mode current is typically 2 mA when a 1 M resistor is not tied between REFOUT and AGND. The AD9831 is tested with a capacitive load of 50 pF. The part can be operated with higher capacitive loads, but the magnitude of the analog output will be attenuated. For example, a 5 MHz output signal will be attenuated by 3 dB when the load capacitance equals 85 pF. Specifications subject to change without notice. RSET 3.9k 10nF REFOUT REFIN FS ADJUST COMP AVDD 10nF ON-BOARD REFERENCE FULL-SCALE CONTROL 12 SIN ROM 10-BIT DAC IOUT 300 50pF AD9831 Figure 1. Test Circuit with Which Specifications Are Tested -2- REV. A AD9831 TIMING CHARACTERISTICS Parameter t1 t2 t3 t4 * t4A* t5 t6 t7 t8 t9 * t9A* t10 Limit at TMIN to TMAX (A Version) 40 16 16 8 8 8 t1 5 3 8 8 t1 (VDD = +3.3 V 10%, +5 V 10%; AGND = DGND = 0 V, unless otherwise noted) Units ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min ns min Test Conditions/Comments MCLK Period MCLK High Duration MCLK Low Duration WR Rising Edge to MCLK Rising Edge WR Rising Edge After MCLK Rising Edge WR Pulse Width Duration between Consecutive WR Pulses Data/Address Setup Time Data/Address Hold Time FSELECT, PSEL0, PSEL1 Setup Time Before MCLK Rising Edge FSELECT, PSEL0, PSEL1 Setup Time After MCLK Rising Edge RESET Pulse Duration *See Pin Description section. Guaranteed by design but not production tested. t1 MCLK t2 t4A WR t3 t5 t4 t6 Figure 2. Clock Synchronization Timing t6 t5 WR t8 t7 A0, A1, A2 DATA VALID DATA VALID DATA Figure 3. Parallel Timing MCLK t9 FSELECT PSEL0, PSEL1 VALID DATA VALID DATA t9A VALID DATA t10 RESET Figure 4. Control Timing REV. A -3- AD9831 ABSOLUTE MAXIMUM RATINGS* (TA = +25C unless otherwise noted) PIN CONFIGURATION FS ADJUST AVDD to AGND . . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +7 V AVDD to DVDD . . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V AGND to DGND. . . . . . . . . . . . . . . . . . . . . . -0.3 V to +0.3 V Digital I/O Voltage to DGND . . . . . -0.3 V to DVDD + 0.3 V Analog I/O Voltage to AGND . . . . . -0.3 V to AVDD + 0.3 V Operating Temperature Range Industrial (A Version) . . . . . . . . . . . . . . . . -40C to +85C Storage Temperature Range . . . . . . . . . . . . -65C to +150C Maximum Junction Temperature . . . . . . . . . . . . . . . . +150C TQFP JA Thermal Impedance . . . . . . . . . . . . . . . . . 75C/W Lead Temperature, Soldering Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . . . +215C Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . +220C ESD Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . > 4500 V *Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. COMP REFIN AGND AVDD AVDD NC AVDD IOUT 48 47 46 45 44 43 42 41 40 39 38 37 AGND 1 REFOUT 2 SLEEP 3 DVDD 4 DVDD 5 DGND 6 MCLK 7 WR 8 DVDD 9 FSELECT 10 PSEL0 11 PSEL1 12 13 14 15 16 17 18 19 20 21 22 23 24 PIN 1 IDENTIFIER NC NC NC 36 35 34 33 32 AGND RESET A0 A1 A2 DB0 DB1 DGND DB2 DB3 DB4 DVDD AD9831 TOP VIEW (Not to Scale) 31 30 29 28 27 26 25 DGND DB15 DB14 DB13 DB12 DB10 NC = NO CONNECT ORDERING GUIDE Model Temperature Range Package Package Description Option* AD9831AST - 40C to +85C 48-Pin TQFP ST-48 EVAL-AD9831EB Evaluation Board *ST = Thin Quad Flatpack (TQFP). DB11 DB9 DB8 DB7 DB6 DB5 -4- REV. A AD9831 PIN DESCRIPTION Mnemonic Function POWER SUPPLY AVDD Positive power supply for the analog section. A 0.1 F decoupling capacitor should be connected between AVDD and AGND. AVDD can have a value of +5 V 10% or +3.3 V 10%. AGND Analog Ground. DVDD Positive power supply for the digital section. A 0.1 F decoupling capacitor should be connected between DVDD and DGND. DVDD can have a value of +5 V 10% or +3.3 V 10%. DGND Digital Ground. ANALOG SIGNAL AND REFERENCE IOUT Current Output. This is a high impedance current source. A load resistor should be connected between IOUT and AGND. FS ADJUST Full-Scale Adjust Control. A resistor (RSET) is connected between this pin and AGND. This determines the magnitude of the full-scale DAC current. The relationship between RSET and the full-scale current is as follows: IOUTFULL-SCALE = 12.5 x VREFIN/RSET VREFIN = 1.21 V nominal, RSET = 3.9 k typical REFIN Voltage Reference Input. The AD9831 can be used with either the on-board reference, which is available from pin REFOUT, or an external reference. The reference to be used is connected to the REFIN pin. The AD9831 accepts a reference of 1.21 V nominal. REFOUT Voltage Reference Output. The AD9831 has an on-board reference of value 1.21 V nominal. The reference is made available on the REFOUT pin. This reference is used as the reference to the DAC by connecting REFOUT to REFIN. REFOUT should be decoupled with a 10 nF capacitor to AGND. COMP Compensation pin. This is a compensation pin for the internal reference amplifier. A 10 nF decoupling ceramic capacitor should be connected between COMP and AVDD. DIGITAL INTERFACE AND CONTROL MCLK Digital Clock Input. DDS output frequencies are expressed as a binary fraction of the frequency of MCLK. The output frequency accuracy and phase noise are determined by this clock. FSELECT Frequency Select Input. FSELECT controls which frequency register, FREQ0 or FREQ1, is used in the phase accumulator. FSELECT is sampled on the rising MCLK edge. FSELECT needs to be in steady state when an MCLK rising edge occurs. If FSELECT changes value when a rising edge occurs, there is an uncertainty of one MCLK cycle as to when control is transferred to the other frequency register. To avoid any uncertainty, a change on FSELECT should not coincide with an MCLK rising edge. WR Write, Edge-Triggered Digital Input. The WR pin is used when writing data to the AD9831. The data is loaded into the AD9831 on the rising edge of the WR pulse. This data is then loaded into the destination register on the MCLK rising edge. The WR pulse rising edge should not coincide with the MCLK rising edge as there will be an uncertainty of one MCLK cycle regarding the loading of the destination register with the new data. The WR rising edge should occur before an MCLK rising edge. The data will then be loaded into the destination register on the MCLK rising edge. Alternatively, the WR rising edge can occur after the MCLK rising edge and the destination register will be loaded on the next MCLK rising edge. D0-D15 Data Bus, Digital Inputs for destination registers. A0-A2 Address Digital Inputs. These address bits are used to select the destination register to which the digital data is to be written. PSEL0, PSEL1 Phase Select Input. The AD9831 has four phase registers. These registers can be used to alter the value being input to the SIN ROM. The contents of the phase register can be added to the phase accumulator output, the inputs PSEL0 and PSEL1 selecting the phase register to be used. Like the FSELECT input, PSEL0 and PSEL1 are sampled on the rising MCLK edge. Therefore, these inputs need to be in steady state when an MCLK rising edge occurs or there is an uncertainty of one MCLK cycle as to when control is transferred to the selected phase register. SLEEP Low Power Control, active low digital input. SLEEP puts the AD9831 into a low power mode. Internal clocks are disabled and the DAC's current sources and REFOUT are turned off. The AD9831 is re-enabled by taking SLEEP high. RESET Reset, active low digital input. RESET resets the phase accumulator to zero which corresponds to an analog output of midscale. REV. A -5- AD9831 TERMINOLOGY Integral Nonlinearity This is the maximum deviation of any code from a straight line passing through the endpoints of the transfer function. The endpoints of the transfer function are zero scale, a point 0.5 LSB below the first code transition (000 . . . 00 to 000 . . . 01) and full scale, a point 0.5 LSB above the last code transition (111 . . . 10 to 111 . . . 11). The error is expressed in LSBs. Differential Nonlinearity 2 MHz about the fundamental frequency. The narrow band SFDR gives the attenuation of the largest spur or harmonic in a bandwidth of 50 kHz about the fundamental frequency. Clock Feedthrough There will be feedthrough from the MCLK input to the analog output. Clock feedthrough refers to the magnitude of the MCLK signal relative to the fundamental frequency in the AD9831's output spectrum. Table I. Control Registers This is the difference between the measured and ideal 1 LSB change between two adjacent codes in the DAC. Signal to (Noise + Distortion) Register FREQ0 REG Size 32 Bits Description Frequency Register 0. This defines the output frequency, when FSELECT = 0, as a fraction of the MCLK frequency. Frequency Register 1. This defines the output frequency, when FSELECT = 1, as a fraction of the MCLK frequency. Phase Offset Register 0. When PSEL0 = PSEL1 = 0, the contents of this register are added to the output of the phase accumulator. Phase Offset Register 1. When PSEL0 = 1 and PSEL1 = 0, the contents of this register are added to the output of the phase accumulator. Phase Offset Register 2. When PSEL0 = 0 and PSEL1 = 1, the contents of this register are added to the output of the phase accumulator. Phase Offset Register 3. When PSEL0 = PSEL1 = 1, the contents of this register are added to the output of the phase accumulator. Signal to (Noise + Distortion) is measured signal to noise at the output of the DAC. The signal is the rms magnitude of the fundamental. Noise is the rms sum of all the nonfundamental signals up to half the sampling frequency (fMCLK/2) but excluding the dc component. Signal to (Noise + Distortion) is dependent on the number of quantization levels used in the digitization process; the more levels, the smaller the quantization noise. The theoretical Signal to (Noise + Distortion) ratio for a sine wave input is given by Signal to (Noise + Distortion) = (6.02N + 1.76) dB where N is the number of bits. Thus, for an ideal 10-bit converter, Signal to (Noise + Distortion) = 61.96 dB. Total Harmonic Distortion FREQ1 REG 32 Bits PHASE0 REG 12 Bits PHASE1 REG 12 Bits Total Harmonic Distortion (THD) is the ratio of the rms sum of harmonics to the rms value of the fundamental. For the AD9831, THD is defined as THD = 20 log 2 (V 2 +V 3 2 2 +V 4 +V 5 2 PHASE2 REG 12 Bits +V 6 2 V1 where V1 is the rms amplitude of the fundamental and V2, V3, V4, V5 and V6 are the rms amplitudes of the second through the sixth harmonic. Output Compliance PHASE3 REG 12 Bits The output compliance refers to the maximum voltage which can be generated at the output of the DAC to meet the specifications. When voltages greater than that specified for the output compliance are generated, the AD9831 may not meet the specifications listed in the data sheet. Spurious Free Dynamic Range Table II. Addressing the Control Registers A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 Destination Register FREQ0 REG 16 LSBs FREQ0 REG 16 MSBs FREQ1 REG 16 LSBs FREQ1 REG 16 MSBs PHASE0 REG PHASE1 REG PHASE2 REG PHASE3 REG Along with the frequency of interest, harmonics of the fundamental frequency and images of the MCLK frequency are present at the output of a DDS device. The spurious free dynamic range (SFDR) refers to the largest spur or harmonic which is present in the band of interest. The wide band SFDR gives the magnitude of the largest harmonic or spur relative to the magnitude of the fundamental frequency in the bandwidth Table III. Frequency Register Bits D15 MSB D0 LSB Table IV. Phase Register Bits D15 X D14 X D13 X D12 X D11 MSB D0 LSB -6- REV. A Typical Performance Characteristics-AD9831 25 TA = +25C 20 TOTAL CURRENT - mA -50 SFDR (2MHz) - dB +5V 15 25MHz -55 10MHz -60 -65 -70 5 -75 0 -80 -40 AVDD = DVDD = +3.3V -45 10 +3.3V 5 10 15 20 MCLK FREQUENCY - MHz 25 0 0.1 0.2 fOUT/fMCLK 0.3 0.4 Figure 5. Typical Current Consumption vs. MCLK Frequency Figure 8. Wide Band SFDR vs. fOUT/fMCLK for Various MCLK Frequencies -50 fOUT/fMCLK = 1/3 AVDD = DVDD = +3.3V -55 60 AVDD = DVDD = +3.3V fOUT = fMCLK/3 55 SFDR (50kHz) - dB -60 SNR - dB 15 20 MCLK FREQUENCY - MHz 25 -65 50 -70 45 -75 -80 10 40 10 15 20 MCLK FREQUENCY - MHz 25 Figure 6. Narrow Band SFDR vs. MCLK Frequency Figure 9. SNR vs. MCLK Frequency -40 fOUT/fMCLK = 1/3 AVDD = DVDD = +3.3V -45 60 AVDD = DVDD = +3.3V 55 SFDR (2MHz) - dB 10MHz -50 SNR - dB 50 25MHz -55 45 -60 -65 10 15 20 MCLK FREQUENCY - MHz 25 40 0 0.1 0.2 fOUT/fMCLK 0.3 0.4 Figure 7. Wide Band SFDR vs. MCLK Frequency Figure 10. SNR vs. fOUT/fMCLK for Various MCLK Frequencies REV. A -7- AD9831-Typical Performance Characteristics 10 AVDD = DVDD = +2.97V 0 -10 -20 7.5 WAKE-UP TIME - ms -30 10dB/DIV -40 -50 -60 -70 5.0 2.5 -80 -90 0 -40 -100 -30 -20 TEMPERATURE - C -10 0 START 0Hz RBW 300Hz VBW 1kHz STOP 12.5MHz ST 277 SEC Figure 11. Wake-Up Time vs. Temperature Figure 14. fMCLK = 25 MHz, fOUT = 3.1 MHz, Frequency Word = 1FBE76C9 0 -10 -20 -30 0 -10 -20 -30 10dB/DIV -40 -50 -60 -70 -80 -90 -100 10dB/DIV -40 -50 -60 -70 -80 -90 -100 START 0Hz RBW 300Hz VBW 1kHz STOP 12.5MHz ST 277 SEC START 0Hz RBW 300Hz VBW 1kHz STOP 12.5MHz ST 277 SEC Figure 12. fMCLK = 25 MHz, fOUT = 1.1 MHz, Frequency Word = B439581 Figure 15. fMCLK = 25 MHz, fOUT = 4.1 MHz, Frequency Word = 29FBE76D 0 -10 -20 -30 10dB/DIV 10dB/DIV 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 START 0Hz RBW 300Hz VBW 1kHz STOP 12.5MHz ST 277 SEC START 0Hz RBW 300Hz VBW 1kHz STOP 12.5MHz ST 277 SEC -40 -50 -60 -70 -80 -90 -100 Figure 13. fMCLK = 25 MHz, fOUT = 2.1 MHz, Frequency Word = 15810625 Figure 16. fMCLK = 25 MHz, fOUT = 5.1 MHz, Frequency Word = 34395810 -8- REV. A AD9831 0 -10 -20 -30 10dB/DIV 10dB/DIV -40 -50 -60 -70 -80 -90 -100 START 0Hz RBW 300Hz VBW 1kHz STOP 12.5MHz ST 277 SEC 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 START 0Hz RBW 300Hz VBW 1kHz STOP 12.5MHz ST 277 SEC Figure 17. fMCLK = 25 MHz, fOUT = 6.1 MHz, Frequency Word = 3E76C8B4 Figure 19. fMCLK = 25 MHz, fOUT = 8.1 MHz, Frequency Word = 52F1A9FC 0 -10 -20 -30 10dB/DIV 10dB/DIV 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 START 0Hz RBW 300Hz VBW 1kHz STOP 12.5MHz ST 277 SEC START 0Hz RBW 300Hz VBW 1kHz STOP 12.5MHz ST 277 SEC -40 -50 -60 -70 -80 -90 -100 Figure 18. fMCLK = 25 MHz, fOUT = 7.1 MHz, Frequency Word = 48B43958 Figure 20. fMCLK = 25 MHz, fOUT = 9.1 MHz, Frequency Word = 5D2F1AA0 REV. A -9- AD9831 CIRCUIT DESCRIPTION Numerical Controlled Oscillator + Phase Modulator The AD9831 provides an exciting new level of integration for the RF/Communications system designer. The AD9831 combines the Numerical Controlled Oscillator (NCO), SINE LookUp Table, Frequency and Phase Modulators, and a Digital-toAnalog Converter on a single integrated circuit. The internal circuitry of the AD9831 consists of three main sections. These are: Numerical Controlled Oscillator (NCO) + Phase Modulator SINE Look-Up Table Digital-to-Analog Converter The AD9831 is a fully integrated Direct Digital Synthesis (DDS) chip. The chip requires one reference clock, one low precision resistor and eight decoupling capacitors to provide digitally created sine waves up to 12.5 MHz. In addition to the generation of this RF signal, the chip is fully capable of a broad range of simple and complex modulation schemes. These modulation schemes are fully implemented in the digital domain allowing accurate and simple realization of complex modulation algorithms using DSP techniques. THEORY OF OPERATION This consists of two frequency select registers, a phase accumulator and four phase offset registers. The main component of the NCO is a 32-bit phase accumulator which assembles the phase component of the output signal. Continuous time signals have a phase range of 0 to 2. Outside this range of numbers, the sinusoid functions repeat themselves in a periodic manner. The digital implementation is no different. The accumulator simply scales the range of phase numbers into a multibit digital word. The phase accumulator in the AD9831 is implemented with 32 bits. Therefore, in the AD9831, 2 = 232. Likewise, the Phase term is scaled into this range of numbers 0 < Phase < 232 - 1. Making these substitutions into the equation above f = Phase x fMCLK/232 where 0 < Phase < 232 With a clock signal of 25 MHz and a phase word of 051EB852 hex f = 51EB852 x 25 MHz/232 = 0.500000000465 MHz The input to the phase accumulator (i.e., the phase step) can be selected either from the FREQ0 Register or FREQ1 Register and this is controlled by the FSELECT pin. NCOs inherently generate continuous phase signals, thus avoiding any output discontinuity when switching between frequencies. Following the NCO, a phase offset can be added to perform phase modulation using the 12-bit PHASE Registers. The contents of this register are added to the most significant bits of the NCO. The AD9831 has four PHASE registers, the resolution of these registers being 2/4096. Sine Look-Up Table (LUT) Sine waves are typically thought of in terms of their magnitude form a(t) = sin (t). However, these are nonlinear and not easy to generate except through piece wise construction. On the other hand, the angular information is linear in nature. That is, the phase angle rotates through a fixed angle for each unit of time. The angular rate depends on the frequency of the signal by the traditional rate of = 2f. MAGNITUDE +1 0 -1 PHASE 2 To make the output useful, the signal must be converted from phase information into a sinusoidal value. Since phase information maps directly into amplitude, a ROM LUT converts the phase information into amplitude. To do this, the digital phase information is used to address a sine ROM LUT. Although the NCO contains a 32-bit phase accumulator, the output of the NCO is truncated to 12 bits. Using the full resolution of the phase accumulator is impractical and unnecessary as this would require a look-up table of 232 entries. It is necessary only to have sufficient phase resolution in the LUTs such that the dc error of the output waveform is dominated by the quantization error in the DAC. This requires the look-up table to have two more bits of phase resolution than the 10-bit DAC. Digital-to-Analog Converter 0 Figure 21. Sine Wave Knowing that the phase of a sine wave is linear and given a reference interval (clock period), the phase rotation for that period can be determined. Phase = t Solving for = Phase/t = 2f Solving for f and substituting the reference clock frequency for the reference period (1/fMCLK = t) f = Phase x fMCLK/2 The AD9831 builds the output based on this simple equation. A simple DDS chip can implement this equation with three major subcircuits. The AD9831 includes a high impedance current source 10-bit DAC, capable of driving a wide range of loads at different speeds. Full-scale output current can be adjusted, for optimum power and external load requirements, through the use of a single external resistor (RSET). The DAC is configured for single ended operation. The load resistor can be any value required, as long as the full-scale voltage developed across it does not exceed the voltage compliance range. Since full-scale current is controlled by RSET, adjustments to RSET can balance changes made to the load resistor. However, if the DAC full-scale output current is significantly less than 4 mA, the DAC's linearity may degrade. -10- REV. A AD9831 DSP and MPU Interfacing The AD9831 has a parallel interface, with 16 bits of data being loaded during each write cycle. The frequency or phase registers are loaded by asserting the WR signal. The destination register for the 16 bit data is selected using the address inputs A0, A1 and A2. The phase registers are 12 bits wide so, only the 12 LSBs need to be valid--the 4 MSBs of the 16 bit word do not have to contain valid data. Data is loaded into the AD9831 by pulsing WR low, the data being latched into the AD9831 on the rising edge of WR. The values of inputs A0, A1 and A2 are also latched into the AD9831 on the WR rising edge. The appropriate destination register is updated on the next MCLK rising edge. If the WR rising edge coincides with the MCLK rising edge, there is an uncertainty of one MCLK cycle regarding the loading of the destination register--the destination register may be loaded immediately or the destination register may be updated on the next MCLK rising edge. To avoid any uncertainty, the times listed in the specifications should be complied with. FSELECT, PSEL0 and PSEL1 are sampled on the MCLK rising edge. Again, these inputs should be valid when an MCLK rising edge occurs as there will be an uncertainty of one MCLK cycle introduced otherwise. When these inputs change value, there will be a pipeline delay before control is transferred to the selected register--there will be a pipeline delay before the analog output is controlled by the selected register. There is a similar delay when a new word is written to a register. PSEL0, PSEL1, FSELECT and WR have latencies of six MCLK cycles. The flow chart in Figure 22 shows the operating routine for the AD9831. When the AD9831 is powered up, the part should be reset using RESET. This will reset the phase accumulator to zero so that the analog output is at midscale. RESET does not reset the phase and frequency registers. These registers will contain invalid data and, therefore, should be set to zero by the user. The registers to be used should be loaded, the analog output being fMCLK/232 x FREG where FREG is the value loaded into the selected frequency register. This signal will be phase shifted by the amount specified in the selected phase register (2/4096 x PHASEREG where PHASEREG is the value contained in the selected phase register). When FSELECT, PSEL0 and PSEL1 are programmed, there will be a pipeline delay of approximately 6 MCLK cycles before the analog output reacts to the change on these inputs. RESET DATA WRITE FREG<0, 1> = 0 PHASEREG<0, 1, 2, 3> = 0 DATA WRITE FREG<0> = fOUT0/fMCLK*232 FREG<1> = fOUT1/fMCLK*232 PHASEREG<3:0> = DELTA PHASE<0, 1, 2, 3> SELECT DATA SOURCES SET FSELECT SET PSEL0, PSEL1 WAIT 6 MCLK CYCLES DAC OUTPUT VOUT = VREFIN*6.25*ROUT/RSET*(1 + SIN(2(FREG*fMCLK*t/232 + PHASEREG/212))) YES CHANGE PHASE? NO NO CHANGE FOUT? YES NO CHANGE FSELECT CHANGE FREG? YES CHANGE PHASEREG? YES NO CHANGE PSEL0, PSEL1 Figure 22. Flow Chart for AD9831 Initialization and Operation REV. A -11- AD9831 APPLICATIONS The AD9831 contains functions which make it suitable for modulation applications. The part can be used to perform simple modulation such as FSK. More complex modulation schemes such as GMSK and QPSK can also be implemented using the AD9831. In an FSK application, the two frequency registers of the AD9831 are loaded with different values; one frequency will represent the space frequency while the other will represent the mark frequency. The digital data stream is fed to the FSELECT pin which will cause the AD9831 to modulate the carrier frequency between the two values. The AD9831 has four phase registers; this enables the part to perform PSK. With phase shift keying, the carrier frequency is phase shifted, the phase being altered by an amount which is related to the bit stream being input to the modulator. The presence of four shift registers eases the interaction needed between the DSP and the AD9831. The frequency and phase registers can be written to continuously, if required. The maximum update rate equals the frequency of the MCLK. However, if a selected register is loaded with a new word, there will be a delay of 6 MCLK cycles before the analog output will change accordingly. The AD9831 is also suitable for signal generator applications. With its low current consumption, the part is suitable for applications in which it can be used as a local oscillator. In addition, the part is fully specified for operation with a +3.3 V 10% power supply. Therefore, in portable applications where current consumption is an important issue, the AD9831 is perfect. Grounding and Layout device requiring an AGND to DGND connection, then the ground planes should be connected at the AGND and DGND pins of the AD9831. If the AD9831 is in a system where multiple devices require AGND to DGND connections, the connection should be made at one point only, a star ground point that should be established as close as possible to the AD9831. Avoid running digital lines under the device as these will couple noise onto the die. The analog ground plane should be allowed to run under the AD9831 to avoid noise coupling. The power supply lines to the AD9831 should use as large a track as is possible to provide low impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other sections of the board. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This will reduce the effects of feedthrough through the board. A microstrip technique is by far the best but is not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground planes while signals are placed on the other side. Good decoupling is important. The analog and digital supplies to the AD9831 are independent and separately pinned out to minimize coupling between analog and digital sections of the device. All analog and digital supplies should be decoupled to AGND and DGND respectively with 0.1 F ceramic capacitors in parallel with 10 F tantalum capacitors. To achieve the best from the decoupling capacitors, they should be placed as close as possible to the device, ideally right up against the device. In systems where a common supply is used to drive both the AVDD and DVDD of the AD9831, it is recommended that the system's AVDD supply be used. This supply should have the recommended analog supply decoupling between the AVDD pins of the AD9831 and AGND and the recommended digital supply decoupling capacitors between the DVDD pins and DGND. The printed circuit board that houses the AD9831 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. This facilitates the use of ground planes which can be separated easily. A minimum etch technique is generally best for ground planes as it gives the best shielding. Digital and analog ground planes should only be joined in one place. If the AD9831 is the only -12- REV. A AD9831 AD9831 Evaluation Board Using the AD9831 Evaluation Board The AD9831 Evaluation Board allows designers to evaluate the high performance AD9831 DDS Modulator with a minimum of effort. To prove that this device will meet the user's waveform synthesis requirements, the user only requires a 3.3 V or 5 V power supply, an IBM-compatible PC and a spectrum analyzer along with the evaluation board. The evaluation setup is shown below. The DDS Evaluation kit includes a populated, tested AD9831 printed circuit board along with the software which controls the AD9831 in a Windows environment. IBM COMPATIBLE PC PARALLEL PORT CENTRONICS PRINTER CABLE AD9831.EXE The AD9831 Evaluation kit is a test system designed to simplify the evaluation of the AD9831. Provisions to control the AD9831 from the printer port of an IBM-compatible PC are included along with the necessary software. An application note is also available with the evaluation board which gives information on operating the evaluation board. Prototyping Area An area is available on the evaluation board where the user can add additional circuits to the evaluation test set. Users may want to build custom analog filters for the output or add buffers and operational amplifiers which are to be used in the final application. XO vs. External Clock AD9831 EVALUATION BOARD The AD9831 can operate with master clocks up to 25 MHz. A 25 MHz oscillator is included on the evaluation board. However, this oscillator can be removed and an external CMOS clock connected to the part, if required. Power Supply Figure 23. AD9831 Evaluation Board Setup Power to the AD9831 Evaluation Board must be provided externally through the pin connections. The power leads should be twisted to reduce ground loops. REV. A -13- AD9831 DVDD C1, C2, C3 0.1F 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 DVDD LATCH D0 D1 D2 D3 D4 D5 D6 D7 C14 0.1F VDD DVDD 4, 5, 9, 25 14 D15 D15 42 C7 10nF AVDD 38, 43, 47 AVDD AVDD C4, C5, C6 0.1F U2 J1 PC INTERFACE WR RESET LATCH LOAD D7 DVDD C15 0.1F VDD 74HC574 CK LOAD 21 D8 COMP REFIN 22 D7 REFIN 41 LK5 2 REFOUT C8 10nF U3 74HC574 CK 31 D0 AD9831 U4 RESET D0 LATCH 32 34 8 35 12 A2 A0 WR RESET PSEL1 C10 10F DVDD J2 C9 0.1F J3 C11 0.1F WR R1 10k PSEL1 LK1 PSEL0 LK2 LOAD FSELECT LK3 MCLK DVDD R2 10k R3 10k RESET AVDD C12 10F 11 PSEL0 FSADJUST 40 R5 3.9k IOUT 10 7 FSELECT MCLK IOUT 39 WR DVDD LK4 3 SLEEP DGND 6, 13, 29 AGND 1, 36, 46 R6 300 SW MCLK R4 50 DVDD C13 0.1F DVDD U1 OUT XTAL1 DGND Figure 24. AD9831 Evaluation Board Layout COMPONENT LIST Integrated Circuits XTAL1 U2, U3 U4 Capacitors C1-C6 C7, C8 C9, C11, C13-C15 C10, C12 Resistors R1-R3 R4 R5 R6 OSC XTAL 25 MHz 74HC574 Latches AD9831 (48-Pin TQFP) 0.1 F Ceramic Chip Capacitor 10 nF Ceramic Capacitor 0.1 F Ceramic Capacitor 10 F Tantalum Capacitor 10 k Resistor 50 Resistor 3.9 k Resistor 300 Resistor Links LK1-LK4 LK5 Switch SW Sockets MCLK, PSEL0, PSEL1, FSELECT, IOUT, REFIN Connectors J1 J2, J3 Three Pin Link Two Pin Link End Stackable Switch (SDC Double Throw) Sub-Miniature BNC Connector 36-Pin Edge Connector PCB Mounting Terminal Block -14- REV. A AD9831 OUTLINE DIMENSIONS Dimensions shown in inches and (mm). Thin Quad Flatpack (TQFP) ST-48 0.063 (1.60) MAX 0.030 (0.75) 0.018 (0.45) 0.030 (0.75) 0.057 (1.45) 0.018 (0.45) 0.053 (1.35) 48 1 0.354 (9.00) BSC 0.276 (7.0) BSC 37 36 SEATING PLANE TOP VIEW (PINS DOWN) 0.006 (0.15) 0.002 (0.05) 0 - 7 0 MIN 0.007 (0.18) 0.004 (0.09) 12 13 25 24 0.019 (0.5) BSC 0.011 (0.27) 0.006 (0.17) REV. A -15- 0.354 (9.00) BSC 0.276 (7.0) BSC -16- C2171-12-9/96 PRINTED IN U.S.A. |
Price & Availability of AD9831AST
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